Frequency dividers, such as divide-by-two frequency dividers, receive a clock input at one frequency and deliver an output signal at half the frequency of the clock input. Frequency dividers are used in such applications as phase-locked loops (PLL) and electronic watches. Typical applications focus on designing the frequency dividers to maximize speed or minimize power consumption.
Optimization of frequency dividers for speed or power consumption results in complex circuits with numerous and large electronic components. Such circuits are unsuitable for use in applications where the physical size of the frequency divider is critical. One example of such an application is a pixel driver for a high-resolution liquid-crystal display (LCD). Each pixel driver is associated with an individual pixel in the LCD and applies an in-phase or counter-phase square wave to each pixel. The number of pixels per unit area of the LCD is inversely proportional to the size of the pixel driver circuit. A driver with numerous electronic components results in areal densities below the current LCD requirement of 10,000 pixels per square inch (about 15 pixel/mm2) and much below the higher resolutions which will be required for the next generation of LCDs.
FIGS. 1 and 2 show existing frequency divider circuits. FIG. 1 shows the dynamic frequency divider circuit disclosed in U.S. Pat. No. 5,163,074 to Isobe. The circuit requires at least six transistors. FIG. 2 shows the frequency divider circuit disclosed in U.S. Pat. No. 5,003,566 to Gabillard et al. The circuit requires at least six transistors, plus a diode and a resistor, which are particularly large components.
It would be desirable to have a frequency divider that would overcome the above disadvantages.